data sheet 26180.120 8-bit latched dmos power driver the A6273ka and A6273klw combine eight (positive-edge- triggered d-type) data latches and dmos outputs for systems requiring relatively high load power. driver applications include relays, sole- noids, and other medium-current or high-voltage peripheral power loads. the cmos inputs and latches allow direct interfacing with microproces- sor-based systems. use with ttl may require appropriate pull-up resistors to ensure an input logic high. the dmos output inverts the data input. all of the output drivers are disabled (the dmos sink drivers turned off) with the clear input low. the A6273ka/klw dmos open-drain outputs are capable of sinking up to 750 ma. the A6273ka is furnished in a 20-pin dual in-line plastic package. the A6273klw is furnished in a 20-lead wide-body, small-outline plastic package (soic) with gull-wing leads for surface-mount applica- tions. copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 ma from all outputs continuously, to ambient temperatures over 85 c. features 50 v minimum output clamp voltage 250 ma output current (all outputs simultaneously) 1.3 ? typical r ds(on) low power consumption replacements for tpic6273n and tpic6273dw 6273 note that the A6273ka (dip) and the A6273klw (soic) are electrically identical and share a com- mon terminal number assignment. 1 2 3 8 9 13 14 15 16 17 19 4 5 6 7 12 18 20 in v dd ground out 8 out 7 out 6 dwg. pp-015-2a out 1 out 2 out 3 out 4 out 5 10 11 clear logic supply strobe 8 in 7 in 6 in 5 in 4 in 3 in 2 in 1 latches latches always order by complete part number: part number package r ja r jc A6273ka 20-pin dip 55 c/w 25 c/w A6273klw 20-lead soic 70 c/w 17 c/w absolute maximum ratings at t a = 25 c output voltage, v o ............................. 50 v output drain current, continuous, i o ....................... 250 ma * peak, i om .............................. 750 ma*? peak, i om ..................................... 2.0 a? single-pulse avalanche energy, e as .............................................. 75 mj logic supply voltage, v dd ................ 7.0 v input voltage range, v i ................................. -0.3 v to +7.0 v package power dissipation, p d ........................................ see graph operating temperature range, t a .............................. -40 c to +125 c storage temperature range, t s .............................. -55 c to +150 c * each output, all outputs on. ? pulse duration 100 s, duty cycle 2%. caution: these cmos devices have input static protection (class 3) but are still susceptible to damage if exposed to extremely high static electrical charges.
6273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 copyright ? 2002 allegro microsystems, inc. logic symbol c1 r 1d 4 5 6 7 14 15 16 17 1 2 11 dw g . fp-046-1a 1d 3 1d 8 1d 9 1d 12 1d 13 1d 18 1d 19 50 75 100 125 150 2.5 0.5 0 allowable package power dissipation in watts ambient temperature in c 2.0 1.5 1.0 25 dwg. gs-004b suffix 'lw', r = 90 c/w ja suffix 'a', r = 55 c/w ja function table inputs clear strobe in x out x lxxh hhl hlh hlxr l = low logic level h = high logic level x = irrelevant r = previous state dmos power driver output logic inputs in dwg. ep-010-16 v dd dwg. ep-063 out
6273 8-bit latched dmos power driver www.allegromicro.com functional block diagram ground dwg. fp-016-2 clear (active low) v dd logic supply out 1 d c1 clr out 2 d c1 clr out 3 d c1 clr out 4 d c1 clr out 5 d c1 clr out 6 d c1 clr out 7 d c1 clr out 8 d c1 clr 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8 in strobe
6273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 limits characteristic symbol test conditions min. typ. max. units logic supply voltage v dd operating 4.5 5.0 5.5 v output breakdown v (br)dsx i o = 1 ma 50 v voltage off-state output i dsx v o = 40 v 0.05 1.0 a current v o = 40 v t a = 125 c 0.15 5.0 a static drain-source r ds(on) i o = 250 ma, v dd = 4.5 v 1.3 2.0 ? on-state resistance i o = 250 ma, v dd = 4.5 v, t a = 125 c 2.0 3.2 ? i o = 500 ma, v dd = 4.5 v (see note) 1.3 2.0 ? nominal output i o(nom) v ds(on) = 0.5 v, t a = 85 c 250 ma current logic input current i ih v i = v dd = 5.5 v 1.0 a i il v i = 0, v dd = 5.5 v -1.0 a prop. delay time t plh i o = 250 ma, c l = 30 pf 625 ns t phl i o = 250 ma, c l = 30 pf 150 ns output rise time t r i o = 250 ma, c l = 30 pf 675 ns output fall time t f i o = 250 ma, c l = 30 pf 400 ns supply current i dd(off) v dd = 5.5 v, outputs off 15 100 a i dd(on) v dd = 5.5 v, outputs on 150 300 a typical data is at v dd = 5 v and is for design information only. note pulse test, duration 100 s, duty cycle 2%. electrical characteristics at t a = +25 c, v dd = 5 v, t ir = t if 10 ns (unless otherwise specified). recommended operating conditions over operating temperature range logic supply voltage range, v dd ............... 4.5 v to 5.5 v high-level input voltage, v ih ............................ 0.85v dd low-level input voltage, v il ................................. 0.15v dd
6273 8-bit latched dmos power driver www.allegromicro.com timing requirements phl t 90% f t 50% su(d) t plh t 50% outputx dwg. wp-036-1 10% r t inx strobe h(d) t 50% su(d) t h(d) t input active time before strobe (data set-up time), t su(d) .............................................. 20 ns input active time after strobe (data hold time), t h(d) ................................................... 20 ns input pulse width, t w(d) ...................................................... 40 ns input logic high, v ih ................................................ 0.85v dd input logic low, v il ................................................. 0.15v dd test circuit dwg. ep-066-1 out input i o v o t av i as = 1.0 a v (br)dsx v o(on) 0.11 ? 100 mh +15 v dut single-pulse avalanche energy test circuit and waveforms e as = i as x v (br)dsx x t av /2
6273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 terminal descriptions terminal no. terminal name function 1 clear when (active) low, all latches are reset and all outputs go high (turn off). 2 in 1 cmos data input to a latch. when strobed, the output then inverts the data input (in 1 = high, out 1 = low). 3 in 2 cmos data input to a latch. when strobed, the output then inverts the data input (in 2 = high, out 2 = low). 4 out 1 current-sinking, open-drain dmos output. 5 out 2 current-sinking, open-drain dmos output. 6 out 3 current-sinking, open-drain dmos output. 7 out 4 current-sinking, open-drain dmos output. 8 in 3 cmos data input to a latch. when strobed, the output then inverts the data input (in 3 = high, out 3 = low). 9 in 4 cmos data input to a latch. when strobed, the output then inverts the data input (in 4 = high, out 4 = low). 10 ground reference terminal for all voltage measurements. 11 strobe a cmos dynamic input to all latches. data on each in x terminal is loaded into its associated latch on a low-to-high strobe transition. 12 in 5 cmos data input to a latch. when strobed, the output then inverts the data input (in 5 = high, out 5 = low). 13 in 6 cmos data input to a latch. when strobed, the output then inverts the data input (in 6 = high, out 6 = low). 14 out 5 current-sinking, open-drain dmos output. 15 out 6 current-sinking, open-drain dmos output. 16 out 7 current-sinking, open-drain dmos output. 17 out 8 current-sinking, open-drain dmos output. 18 in 7 cmos data input to a latch. when strobed, the output then inverts the data input (in 7 = high, out 7 = low). 19 in 8 cmos data input to a latch. when strobed, the output then inverts the data input (in 8 = high, out 8 = low). 20 logic supply (v dd ) the logic supply voltage (typically 5 v).
6273 8-bit latched dmos power driver www.allegromicro.com A6273ka dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) notes:1. exact body and lead configuration at vendors option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. lead thickness is measured at seating plane or below. 4. supplied in standard sticks/tubes of 18 devices. 0.355 0.204 7.62 bsc dwg. ma-001-20 mm 10.92 max 20 1 10 7.11 6.10 5.33 max 1.77 1.15 0.39 min 0.558 0.356 2.54 bsc 0.13 min 3.81 2.93 11 26.92 24.89 0.014 0.008 0.300 bsc dwg. ma-001-20 in 0.430 max 20 1 10 0.280 0.240 0.210 max 0.070 0.045 0.015 min 0.022 0.014 0.100 bsc 0.005 min 0.150 0.115 11 1.060 0.980
6273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 A6273klw dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions) 0 to 8 1 2 3 0.020 0.013 0.0040 min. 0.0125 0.0091 0.050 0.016 dwg. ma-008-20 in 0.050 bsc 20 11 0.2992 0.2914 0.419 0.394 0.5118 0.4961 0.0926 0.1043 0 to 8 1 20 2 3 0.51 0.33 0.10 min. dwg. ma-008-20 mm 1.27 bsc 11 0.32 0.23 1.27 0.40 7.60 7.40 10.65 10.00 13.00 12.60 2.65 2.35 notes:1. exact body and lead configuration at vendors option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. supplied in standard sticks/tubes of 37 devices or add tr to part number for tape and reel.
6273 8-bit latched dmos power driver www.allegromicro.com the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
6273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 power interface drivers function output ratings* part number ? serial-input latched drivers 8-bit (saturated drivers) -120 ma 50 v? 5895 8-bit 350 ma 50 v 5821 8-bit 350 ma 80 v 5822 8-bit 350 ma 50 v? 5841 8-bit 350 ma 80 v? 5842 8-bit (constant-current led driver) 75 ma 17 v 6275 8-bit (constant-current led driver) 120 ma 24 v 6277 8-bit (dmos drivers) 250 ma 50 v 6595 8-bit (dmos drivers) 350 ma 50 v? 6a595 8-bit (dmos drivers) 100 ma 50 v 6b595 10-bit (active pull-downs) -25 ma 60 v 5810-f and 6810 12-bit (active pull-downs) -25 ma 60 v 5811 16-bit (constant-current led driver) 75 ma 17 v 6276 20-bit (active pull-downs) -25 ma 60 v 5812-f and 6812 32-bit (active pull-downs) -25 ma 60 v 5818-f and 6818 32-bit 100 ma 30 v 5833 32-bit (saturated drivers) 100 ma 40 v 5832 parallel-input latched drivers 4-bit 350 ma 50 v? 5800 8-bit -25 ma 60 v 5815 8-bit 350 ma 50 v? 5801 8-bit (dmos drivers) 100 ma 50 v 6b273 8-bit (dmos drivers) 250 ma 50 v 6273 special-purpose devices unipolar stepper motor translator/driver 1.25 a 50 v? 5804 addressable 8-bit decoder/dmos driver 250 ma 50 v 6259 addressable 8-bit decoder/dmos driver 350 ma 50 v? 6a259 addressable 8-bit decoder/dmos driver 100 ma 50 v 6b259 addressable 28-line decoder/driver 450 ma 30 v 6817 * current is maximum specified test condition, voltage is maximum rating. see specification for sustaining voltage limits. negative current is defined as coming out of (sourcing) the output. ? complete part number includes additional characters to indicate operating temperature range and package style. internal transient-suppression diodes included for inductive-load protection.
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